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SM8223A/B
NIPPON PRECISION CIRCUITS INC.
FSK Decoder and DTMF Receiver IC
OVERVIEW
The SM8223A/B is a FSK (Frequency shift keying) decoder and DTMF (Dual tone multi-frequency) receiver IC. It is fabricated using a CMOS process and features a power-down function for low power dissipation operation. The FSK decoder and DTMF receiver have the same performance characteristics as dedicated ICs that perform the same functions, with the added benefit of an FSK decoder/DTMF receiver auto-select function1 using the telephone tip/ring input signal. It also features a ring (call signal) signal detection circuit, making for easy construction of low power dissipation, high-performance analog telephone-related applications.
FEATURES
s
PINOUT
(Unit: mm)
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s s s s s
s
s
s
Both FSK signal caller-ID information services and DTMF signal caller-ID information services supported FSK decoder/DTMF receiver auto-select function Ring (call signal) signal detection circuit built-in Serial I/O Input gain adjustment circuit built-in Power-down mode Single supply operation * SM8223A: 3.0V 10% * SM8223B: 5.0V 10% 3.579545MHz external crystal oscillator frequency Molybdenum-gate CMOS process
APPLICATIONS
s
s
s
Telephones, fax machines and modems that support caller-ID information services Adapters for caller-ID information service functions Telephones, fax machines and modems that support remote operation functions
ORDERING INFORMATION
D e vice
P ackag e
SM8223A/B
16-pin DIP
1. Auto-select function operates if the FSK signal conforms to the Bellcore GR-30-CORE standard.
NIPPON PRECISION CIRCUITS--1
ry
TIP
1 16
VDD DV DOUT FSK/DTMF IC OSCIN OSCOUT GND
SM8223 P
RING GS
AGND RDIN
RDRC RDET
PDWN
8
9
SM8223A/B
PACKAGE DIMENSIONS
(Unit: mm)
7.49 to 8.13
3.18
3.30
2.54
0.46
1.52
BLOCK DIAGRAM
FSK/DTMF
Differential Amplifier
TIP RING GS
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FSK Decoder
Band Pass Filter High Group Filter Dial Tone Filter Low Group Filter
0.38 to 1.02 3.68 to 4.32
0.25
19.05
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FSK/DTMF Discriminator Logic AGND Bias Circuit VDD GND PDWN OSCIN
DTMF Receiver
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DV FSK Decoder Logic DOUT DTMF Decoder Logic
OSC
Ring Detect
OSCOUT
RDIN
RDRC
RDET
NIPPON PRECISION CIRCUITS--2
8.13 to 9.40
6.35
SM8223A/B
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name TIP RING GS AG N D RDIN RDRC RDET PDW N GND OSCOUT OSCIN IC FSK/ D T M F DOUT DV I/O I I O O I I/O O I - O I I O O O - Function Tip input. Connected to the telephone line through a protection circuit Ring input. Connected to the telephone line through a protection circuit Input-stage amplifier gain-select output. Used to adjust the gain of the input-stage amplifier. Analog ground output. Internal reference voltage (V D D /2) output level
Ring detector input. Used for line reversal and ring signal detection. Connected for ring detection of attenuated ring signals. Ring detector RC terminal. Connected to an RC network which sets the ring detector delay time.
Ring detector output. R D R C -input Schmitt-trigger buffer output. LOW -level output when ring signal is detected. Pow er-down control input. LOW -level for normal operation. HIGH-level for pow er-down state. In the pow er-down state, pins AG N D , O S C O U T, D O U T, and DV are HIGH. Ground. Connected to the system ground potential.
Cr ystal oscillator output. The crystal oscillator element is connected between this pin and OSCIN. Cr ystal oscillator input. The crystal oscillator element is connected between this pin and OSCOUT. Test input. Tied LOW for normal operation.
FSK/DTMF discr iminator output. HIGH-level output when receiving FSK signal, and LOW -level output when receiving DTMF signal. Demodulator output. Demodulated FSK or DTMF signal output. HIGH-level output in pow er-down state. Data trigger output. Data is output on DOUT when this pin goes LOW . Supply
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NIPPON PRECISION CIRCUITS--3
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VDD
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SM8223A/B
SPECIFICATIONS
Absolute Maximum Ratings
GND = 0V
P arameter Supply voltage range Input voltage range Pow er dissipation Storage temperature range Symbol VDD V IN PD Rating -0.5 to 5.0 Unit V V
Recommended Operating Conditions
GND = 0V
P arameter Supply voltage Clock frequency Clock frequency accuracy Operating temperature
Symbol VDD fC L K f C Ta
VDD = 3.0V 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = -20 to 85C unless otherwise noted.
Rating Unit min - typ - max 4.5 mA P arameter Symbol Condition
Supply current consumption
Pow er-down state current
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ID D ID P D V IL1 V IH1 V IL2 V IH2 V IL3 V IH3 IO L IO H IIN IO F F
DC Electrical Characteristics
P D W N L O W -level input voltage
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P D WN, FSK/ D T M F HIGH-level input voltage RDIN, R D R C LOW -level input voltage RDIN, R D R C HIGH-level input voltage O S C I N L OW -level input voltage OSCIN HIGH-level input voltage D O U T, DV, R D E T, FSK/D T M F LOW level output current D O U T, DV, R D E T, FSK/D T M F HIGHlevel output current O S C I N , P DWN, RDIN input leakage current R D R C , FSK/D T M F output leakage current
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- 0.3 to V D D + 0.3 44 T stg -40 to 125 Rating typ - Condition min 2.7 - max 3.3 - 3.579545 - -0.1 -40 +0.1 85 - O S C I N = 0 V, PDW N = 0 V, RDIN = 0 V, R D R C = 0 V, all other inputs open O S C I N = 0 V, PDW N = V D D , RDIN = 0 V, R D R C = 0 V, all other inputs open - - 0.7V D D - 0.7V D D - TBD 2 - -1 - - - - - - - - - - - - 15 0.3V D D - 0.3V D D - TBD - - -0.8 1 1
mW C
Unit V
MHz %
C
A V V V V V V mA mA A A
NIPPON PRECISION CIRCUITS--4
SM8223A/B
AC Electrical Characteristics
FSK decoder VDD = 3.0V 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = -20 to 85C unless otherwise noted.
Rating P arameter Input sensitivity Symbol Condition min -44 - typ max - - -48 -80 -1 0 Unit dBm
Bandpass filter frequency response (gain relative to 1700Hz sine wave input)
DTMF receiver
VDD = 3.0V 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = -20 to 85C unless otherwise noted.
Rating typ - P arameter Detection frequency deviation Non-detection frequency deviation Detection sensitivity Symbol Condition
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Symbol IIN Condition R IN AVOL fC CL RL
Non-detection sensitivity Signal level error
High-frequency rejection ratio Noise rejection ratio
Dial tone rejection ratio
Input-stage amplifier Characteristics
VDD = 3.0V 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = -20 to 85C unless otherwise noted.
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P arameter Input leakage current Input resistance DC open-loop voltage gain Unity gain frequency M a x i m um load capacitance M a x i m um load resistance
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60Hz 1,200Hz - - 2,200Hz 4,000Hz - - - -43 -54 - - 10,000Hz - min max - 1.5% 2 3.5 - - -32.0 - - - - - - 4.0 - - 18 12 20 -40.0 8 - - - Rating min - - TBD TBD - 50 typ - TBD - - - - max 1 - - - TBD -
dB
Unit Hz %
dBm
dBm dB dB dB dB
Unit A M dB MHz pF k
NIPPON PRECISION CIRCUITS--5
SM8223A/B
Timing Characteristics
Oscillator VDD = 3.0V 0.3V, GND = 0V, Ta = -20 to 85C unless otherwise noted.
Rating P arameter Clock HIGH-level pulsewidth Clock LOW -level pulsewidth Clock rise time Clock fall time Symbol tW H tW L tr tf Condition min 110 110 - - typ - - max - - Unit ns ns
FSK decoder
VDD = 3.0V 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = -20 to 85C unless otherwise noted.
Rating typ 8 5 P arameter Pow er-down release time Oscillator start-up time M a r k signal to DV ON time FSK flag setup time FSK flag hold time Symbol tD P D tD O S C tD E D tA F tA H Condition
lim
tA D D tr0 tf0 tI D D Symbol tDr0 tDf0 tR E tR E tPA Condition Q 0 to Q 3 Q 0 to Q 3 DV DV DV DV tP R tB D D tD P D tD O S C tA F
Input to DOUT delay time D O U T r ise time D O U T fall time
Input to DOUT delay time DOUT data rate
DTMF receiver
VDD = 3.0V 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = -20 to 85C unless otherwise noted.
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P arameter D O U T, DV rise time D O U T, DV fall time Signal detection time Received signal non-detection time P ause detection time P ause non-detection time DV output data delay time Pow er-down release time Oscillator start-up time DOUT data rate D T M F fl ag setup time
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- - 30 30 min - - max - - DV = LOW - - 3.75 - 833 (1/1.2kHz) - - - - - 1188 - - 1 - - - 1200 10 5 TBD TBD 5 1212 Rating min - - - 20 20 - - - - 1188 833 (1/1.2kHz) typ - - 35 - - - - 8 5 1200 - max TBD TBD 40 - - 20 5 - - 1212 -
ns ns
Unit ms ms ms ns
ns ms ns ns ms baud
Unit ns ns ms ms ms ms ms ms ms baud ns
NIPPON PRECISION CIRCUITS--6
SM8223A/B OSCIN input timing
tWL
VDD
tWH
OSCIN
VSS
tf
FSK receive timing (1)
1st Ring Tip/Ring
RDET
DV
FSK/DTMF
lim
tDPD tDOSC
Start bit LSB
DOUT
PDWN
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FSK receive timing (2)
Tip/Ring b6 b7 1 0 DOUT
OSCOUT
b4 b5 b6 b7 1
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tr
Ch. seizure Mark Data packet 1010101... 111... Data 2nd Ring
tDED
tAF
tHF
tADD
Data Data output has no Ch.seizure signal.
MSB Stop bit
b0 b1 b2 b3 b4 b5 b6 b7
1
0
b0 b1
tADD
0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1
NIPPON PRECISION CIRCUITS--7
SM8223A/B DOUT output timing
tDWL
DOUT
tDWH
90%
tDf0
DTMF receive timing (1)
Tip/Ring
DTMF Data #1
tRE
DV
tAF
FSK/DTMF
lim
tBDD
Data #1
DOUT
tDPD
PDWN
tDOSC
OSCOUT
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DTMF receive timing (2)
DV DOUT
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tDr0
10%
tPR
tPA
tRE
#1
DTMF Data #2
Data #2
tBDD
0
Q0 Q1 Q2 Q3 S0 S1 S2 S3
1
Start bit
DTMF data
Checksum (2'mod16)
Stop bit
NIPPON PRECISION CIRCUITS--8
SM8223A/B
FUNCTIONAL DESCRIPTION
Ring Signal Detector
The telephone tip and ring signals pass through a protection circuit and are input to a resistor, capacitor and diode bridge network, shown in figure 1.
C2 TIP
R3
C2 RING R3
Db
Figure 1. Ring signal detector circuit The diode bridge full-wave rectified output signal (point a) is reduced in level by a resistor voltage divider comprising R1 and R2 (point b), and then input on RDIN. When the ring signal input on RDIN exceeds the Schmitt buffer trigger voltage (0.7VDD), the output switches the open-drain RDRC pin. The signal at RDRC (point c) drives a time-constant cir-
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NIPPON PRECISION CIRCUITS--9
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a b
D1 R2 RDIN R4 R1 RDRC RDET C1
c
d
cuit comprised by resistor R4 and capacitor C1 connected to the input of a second Schmitt buffer to generate the detector signal output on RDET (point d). Thus, RDET goes LOW when the ring or tip signal exceeds the level set by the resistor voltage divider.
SM8223A/B
VRIG VDD VSS 0.7VDD 0.3VDD
VDD VSS VDD VSS VDD VSS
The voltage divider level and RC time constant are given by the following equations, respectively. R1 + R2 + R3 0.7V DD = -------------------------------- V RIG R3 t C 1 R 4 = ----------------------------------- V DD ln ------------------------- V DD - V T
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where t is the guard time, and the trigger level satisfies the expression 0.3VDD VT 0.7VDD.
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Figure 2. Ring signal detector circuit waveform transitions
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Point a Signal VRIG 0.7VDD 0.3VDD Point b Signal 0.7VDD 0.3VDD Point c Signal 0.7VDD 0.3VDD Point d Signal
NIPPON PRECISION CIRCUITS--10
SM8223A/B
Input Differential Amplifier
The SM8223A/B uses an input differential amplifier for input gain adjustment of the tip/ring signal input to the FSK detector or DTMF receiver. Differential input configuration and single-ended input configuration circuits are shown in figure 3. A bypass capacitor should be connected between GND and AGND in both circuit configurations.
C1 C1
R1 R1 R2 R3 R4 C
TIP RING GS
AGND
Differntial Input
The gain for single-ended configurations is given by the following equation. R2 A V = ----R1
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The gain for differential configurations is given by the following equation, R2 R2 R4 A V = ----- where R 3 = -----------------R1 R2 + R4
FSK/DTMF Auto-discriminator
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The SM8223A/B examines the tip/ring input signal and determines the nature of the signal, FSK or DTMF, and invokes the corresponding circuits, FSK decoder or DTMF receiver, respectively. It determines whether the input signal is an FSK signal or
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TIP C1 R1 RING R2 GS AGND Single-Ended Input C
Figure 3. Input circuits
and the input impedance is given by the following equation.
2 12 Z i = 2 R 1 + ---------- C 1
DTMF signal by the presence or otherwise of the channel seizure information in the FSK signal header. This function automatically discriminates between the input signals if the FSK signal conforms to the Bellcore GR-30-CORE standard.
NIPPON PRECISION CIRCUITS--11
SM8223A/B
FSK Demodulator
When an FSK signal is received, the FSK/DTMF signal discriminator circuit sets the FSK/DTMF pin HIGH and connects the input signal to the FSK demodulator circuit. Demodulated data is output on DOUT with the format shown in figure 4. The FSK signal conforms to the following Bellcore standard.
Table 1. FSK signal
P arameter Modulation type Logic "1" data (mark) Logic "0" data (space) Signal level (mark) Description Continuous-phase binar y frequency-shift keying 1200 12 Hz 2200 22 Hz -32 to -1 2 d B m -36 to -1 2 d B m 1200 12 baud
Start bit
FSK signal
b6 b7
1
DOUT
b4 b5 b6 b7 1
Figure 4. FSK signal to DOUT output
When a DTMF signal is received, the FSK/DTMF signal discriminator circuit sets the FSK/DTMF pin LOW and connects the input signal to the DTMF demodulator circuit. The DTMF signal is comprised by a high-group frequency and a low-group frequency which, in combination, represent a point in the DTMF matrix.
Table 2. DTMF matrix
L o w gro u p 697Hz 770Hz 852Hz 941Hz
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High gro u p 1336Hz 2 5 8 1477Hz 3 6 9 1633Hz A B C D 0 #
DTMF Demodulator
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Signal level (space) Data transfer rate
LSB
MSB Stop bit
0
b0 b1 b2 b3 b4 b5 b6 b7
1
0
b0 b1
0
b0 b1 b2 b3 b4 b5 b6 b7 1
0
b0 b1
Table 3. DTMF signal output (DOUT)
DTMF D0 Q0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D1 Q1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D2 Q2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D3 Q3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D4 S0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Checksum D5 S1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D6 S2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D7 S3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Matrix input 1 2 3 4 5 6 7 8 9 0 * # A B C D
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1 4 7 *
1209Hz
The DTMF receiver demodulates the received DTMF signal and outputs data bits Q0 to Q3 and a 4bit (2-mod-16) checksum S0 to S3 in serial format on DOUT.
NIPPON PRECISION CIRCUITS--12
SM8223A/B
DTMF signal
DTMF DATA
DOUT
0
Q0
Q1
Q2
Q3
S0
S1
S2
S3
1
Figure 5. DTMF signal to DOUT output The DTMF receiver determines whether the received data (DTMF signal) is valid after an interval of tREC 36ms stable reception. If valid, DV goes LOW and data is output on DOUT. If DTMF data is not detected after an interval tSPA 20ms, a data pause is activated and the next DTMF signal is in a
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NIPPON PRECISION CIRCUITS--13
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Start bit DTMF data (LSB first) Checksum (2'mod16) (LSB first) Stop bit
wait state (see timing diagrams in AC Electrical Characteristics). The SM8223A/B DTMF receiver can be used as a general-purpose DTMF receiver without the need for the external time constant circuit, in which case the resistor/capacitor/diode network can be omitted.
SM8223A/B
TYPICAL APPLICATION CIRCUIT
D1 C1 TIP D1 VS D1 C1 RING D1 C3 R6 D2 R1 R1 R2 TIP RING GS VDD DV C6
C3 R6
D2
R1 R2 R3 R4 R5 C1 C2 R6 R7 R8 R9 C3
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TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 3.579545 C4 D2 R 10 R 11 C5 C6 D1 VS X'tal
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TBD TBD TBD TBD TBD TBD TBD TBD TBD k k k k k F F k k k k F F - k k F F - - MHz NIPPON PRECISION CIRCUITS--14
Symbol
Rating
ina ry
R3 R4 R5 DOUT FSK/ DTMF IC AGND RDIN R2 C2 RDRC OSCIN D1 D2 RDET OSCOUT PDWN X'tal R7 R9 GND D2 R8 C4
Unit
SM8223A/B
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698
NP9909AE 1999.09
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NIPPON PRECISION CIRCUITS INC.
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NIPPON PRECISION CIRCUITS--15
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